Presentation	2005/3/3 Low-Power High-Speed 180-nm CMOS Clock Driver Suguru Nagayama, Tadayoshi Enomoto,
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Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	A technique that can minimize both an active power dissipation (P_t) and a delay time (t_ ) of a CMOS clock driver has been developed. The CMOS clock driver that constructed with a three-stage circuit, that is, a single inverter pre-driver stage, an m-parallel inverter driver stage and a resistor stage (consisting of N delay flip flops), has been fabricated using a 180-nm CMOS process technology. By both a SPICE analysis and experimental results obtained by fabricated devices, it was found that both minimum P_t and minimum t_ were obtained by choosing m value of N^<1/2> to 2N^<1/2>.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	CMOS / power dissipation / short-circuit current / delay-time / rise time
Paper #	VLD2004-128,ICD2004-224
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Conference Information
Committee	ICD
Conference Date	2005/3/3(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Low-Power High-Speed 180-nm CMOS Clock Driver
Sub Title (in English)
Keyword(1)	CMOS
Keyword(2)	power dissipation
Keyword(3)	short-circuit current
Keyword(4)	delay-time
Keyword(5)	rise time
1st Author's Name	Suguru Nagayama
1st Author's Affiliation	Graduate School of Science and Engineering, Chuo University()
2nd Author's Name	Tadayoshi Enomoto
2nd Author's Affiliation	Graduate School of Science and Engineering, Chuo University
Date	2005/3/3
Paper #	VLD2004-128,ICD2004-224
Volume (vol)	vol.104
Number (no)	710
Page	pp.pp.-
#Pages	6
Date of Issue