Presentation 2005/3/3
LUT Cascade Realization of FIR Filter
Tsutomu SASAO, Yukihiro IGUCHI, Takahiro SUZUKI,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) This paper first defines the n-input q-output DA function, which denotes the distributed arithmetic for a finite impulse response (FIR) filter. It shows a method to realize the DA function by using k-input q-output cells. The experimental results show that LUT cascade realizations require much smaller memory than the single ROM realization of the DA function.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Digital filter / Distributed arithmetic / LUT cascade / Functional decomposition / Binary decision diagram / FPGA
Paper # VLD2004-126,ICD2004-222
Date of Issue

Conference Information
Committee ICD
Conference Date 2005/3/3(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) LUT Cascade Realization of FIR Filter
Sub Title (in English)
Keyword(1) Digital filter
Keyword(2) Distributed arithmetic
Keyword(3) LUT cascade
Keyword(4) Functional decomposition
Keyword(5) Binary decision diagram
Keyword(6) FPGA
1st Author's Name Tsutomu SASAO
1st Author's Affiliation Department of Computer Science and Electronics, Kyushu Institute of Technology()
2nd Author's Name Yukihiro IGUCHI
2nd Author's Affiliation Department of Computer Science, Meiji University
3rd Author's Name Takahiro SUZUKI
3rd Author's Affiliation Department of Computer Science, Meiji University
Date 2005/3/3
Paper # VLD2004-126,ICD2004-222
Volume (vol) vol.104
Number (no) 710
Page pp.pp.-
#Pages 6
Date of Issue