Presentation | 2005-01-28 New SoC Testing technologies for beyond 65nm process rule : New Failure Analysis and Testing methodologies for low-k/Cu Interconnect technique Makoto YAMAZAKI, Yasuo FURUKAWA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | To solve the problems such as the yield improvements and securing the test quality in the SoC devices made efficient, the adaptive test methodology that optimizes the test condition of each device is already proposed. The structure of new ATE (Automatic Test Equipment) ideas from this adaptive test was shown. A new failure mode will be proposed on low-k/Cu interconnection system that is one of a major steam on beyond 65nm node process. And a new test methodology will be discussed in the actual 0.18um-node ATE LSI. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | ATE / Test / low-k/Cu / Ring-Oscillator / Interconnect technology / ITRS |
Paper # | CPM2004-173,ICD2004-218 |
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Conference Information | |
Committee | ICD |
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Conference Date | 2005/1/21(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | New SoC Testing technologies for beyond 65nm process rule : New Failure Analysis and Testing methodologies for low-k/Cu Interconnect technique |
Sub Title (in English) | |
Keyword(1) | ATE |
Keyword(2) | Test |
Keyword(3) | low-k/Cu |
Keyword(4) | Ring-Oscillator |
Keyword(5) | Interconnect technology |
Keyword(6) | ITRS |
1st Author's Name | Makoto YAMAZAKI |
1st Author's Affiliation | ADVANTEST Corporation() |
2nd Author's Name | Yasuo FURUKAWA |
2nd Author's Affiliation | ADVANTEST Corporation |
Date | 2005-01-28 |
Paper # | CPM2004-173,ICD2004-218 |
Volume (vol) | vol.104 |
Number (no) | 629 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |