| Presentation | 2005-01-28 On Observability Quantification for Fault Diagnosis of VLSI Circuits Naoya TOYOTA, Seiji KAJIHARA, Xiaoqing WEN, Masaru SANADA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In most fault diagnosis, logic values can be observed at primary outputs and scan flip-flops as observation points. However, the diagnostic resolution with these observation points is insufficient. To improve the diagnostic resolution, observation points for fault diagnosis are inserted in the circuit under diagnosis. On the other hand, studies on test point insertion for diagnosis are hard because observability for fault diagnosis has not been quantified. In this paper we discuss on the diagnostic observability of logic circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | fault diagnosis / full scan circuit / test point insertion / observability |
| Paper # | CPM2004-167,ICD2004-212 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2005/1/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On Observability Quantification for Fault Diagnosis of VLSI Circuits |
| Sub Title (in English) | |
| Keyword(1) | fault diagnosis |
| Keyword(2) | full scan circuit |
| Keyword(3) | test point insertion |
| Keyword(4) | observability |
| 1st Author's Name | Naoya TOYOTA |
| 1st Author's Affiliation | Computer Science and Systems Engineering, Kyushu Institute of Technology() |
| 2nd Author's Name | Seiji KAJIHARA |
| 2nd Author's Affiliation | Computer Science and Systems Engineering, Kyushu Institute of Technology |
| 3rd Author's Name | Xiaoqing WEN |
| 3rd Author's Affiliation | Computer Science and Systems Engineering, Kyushu Institute of Technology |
| 4th Author's Name | Masaru SANADA |
| 4th Author's Affiliation | NEC Electronics Test Analysis Technology Development Div. Technology Foundation Development Op. Unit |
| Date | 2005-01-28 |
| Paper # | CPM2004-167,ICD2004-212 |
| Volume (vol) | vol.104 |
| Number (no) | 629 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |