| Presentation | 2005-01-28 Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM Atsushi NAKAYAMA, Toshimasa NAMEKAWA, Hiroshi ITO, FUJII Shuso /, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A post-packaging auto repair technique is implemented in a 36Mb embedded DRAM macro of 6ns cycle time. It consists of internal compare circuit, redundancy analyzer, and anti-fuses. The internal auto programming of anti-fuse fixes post-packaging failures. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | embedded DRAM / BIST / BISR / At-speed test / anti-fuse |
| Paper # | CPM2004-164,ICD2004-209 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2005/1/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM |
| Sub Title (in English) | |
| Keyword(1) | embedded DRAM |
| Keyword(2) | BIST |
| Keyword(3) | BISR |
| Keyword(4) | At-speed test |
| Keyword(5) | anti-fuse |
| 1st Author's Name | Atsushi NAKAYAMA |
| 1st Author's Affiliation | Semiconductor Company, Toshiba Corporation() |
| 2nd Author's Name | Toshimasa NAMEKAWA |
| 2nd Author's Affiliation | Semiconductor Company, Toshiba Corporation |
| 3rd Author's Name | Hiroshi ITO |
| 3rd Author's Affiliation | Semiconductor Company, Toshiba Corporation |
| 4th Author's Name | FUJII Shuso / |
| 4th Author's Affiliation | Semiconductor Company, Toshiba Corporation |
| Date | 2005-01-28 |
| Paper # | CPM2004-164,ICD2004-209 |
| Volume (vol) | vol.104 |
| Number (no) | 629 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |