Presentation 2004/11/25
A State Assignment Method for Constructing Path Delay Faults Detectable Sequential Circuits
Genta SAKUMA, Hiroyuki SHIMAJIRI, Takeo YOSHIDA,
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Abstract(in English) In this paper, we propose a state assignment method for constructing sequential circuits which can detect path delay faults. Path delay faults affect a value of registers in sequential circuits. Therefore, we can detect path delay faults by observing a value of registers in sequential circuits. In this paper, we show detection conditions for path delay faults. We also show a method to satisfy the detection conditions and a design example of path delay faults detectable sequential circuits which are adopted the proposed method. ITC'99 benchmark circuits which are adopted the proposed method had little increase in a delay time.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Path Delay Fault / Fault Detection / Wiring Delay / State Assignment
Paper # VLD2004-76,ICD2004-162,DC2004-62
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Conference Date 2004/11/25(1days)
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Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A State Assignment Method for Constructing Path Delay Faults Detectable Sequential Circuits
Sub Title (in English)
Keyword(1) Path Delay Fault
Keyword(2) Fault Detection
Keyword(3) Wiring Delay
Keyword(4) State Assignment
1st Author's Name Genta SAKUMA
1st Author's Affiliation Department of Information Engineering, Faculty of Engineering, University of the Ryukyus()
2nd Author's Name Hiroyuki SHIMAJIRI
2nd Author's Affiliation Department of Information Engineering, Faculty of Engineering, University of the Ryukyus
3rd Author's Name Takeo YOSHIDA
3rd Author's Affiliation Department of Information Engineering, Faculty of Engineering, University of the Ryukyus
Date 2004/11/25
Paper # VLD2004-76,ICD2004-162,DC2004-62
Volume (vol) vol.104
Number (no) 480
Page pp.pp.-
#Pages 6
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