| Presentation | 2004/11/25 Extraction of Fault Candidate Areas with Layout Information Yoshiteru FUJIMOTO, Hiroyuki YOTSUYANAGI, Masaki HASHIZUME, Takeomi TAMESADA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we present a method for extracting fault candidate areas using layout information obtained by CAD. In highly-integrated circuits, a bridging fault may affect not only between two signal lines, but also among multiple signal lines. In this work, we propose a procesure for extracting fault candidate areas of bridging faults between two lines and bridging faults among three lines. The procedure extracts pairs of signal lines whose distance is within the given distance and identifies them as the fault candidate of a bridging fault, and also extracts groups of three signal lines within the given distance and identifies them as the fault candidate of a multinode bridging fault. The procedure that utilizes a layout information obtained from CAD tools to extract fault candidate areas of bridging faults among two or three lines is shown. The experimental results for benchmark circuits are shown for the comparison between the number of the fault candidate areas obtained by the proposed method and the number of the bridging faults between two lines assumed from gate-level. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | bridging faults / layout information / CAD / multi-node bridge |
| Paper # | VLD2004-74,ICD2004-160,DC2004-60 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2004/11/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Extraction of Fault Candidate Areas with Layout Information |
| Sub Title (in English) | |
| Keyword(1) | bridging faults |
| Keyword(2) | layout information |
| Keyword(3) | CAD |
| Keyword(4) | multi-node bridge |
| 1st Author's Name | Yoshiteru FUJIMOTO |
| 1st Author's Affiliation | Faculty of Engineering, Univ. of Tokushima() |
| 2nd Author's Name | Hiroyuki YOTSUYANAGI |
| 2nd Author's Affiliation | Faculty of Engineering, Univ. of Tokushima |
| 3rd Author's Name | Masaki HASHIZUME |
| 3rd Author's Affiliation | Faculty of Engineering, Univ. of Tokushima |
| 4th Author's Name | Takeomi TAMESADA |
| 4th Author's Affiliation | Faculty of Engineering, Univ. of Tokushima |
| Date | 2004/11/25 |
| Paper # | VLD2004-74,ICD2004-160,DC2004-60 |
| Volume (vol) | vol.104 |
| Number (no) | 480 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |