| Presentation | 2004/11/25 Design for Testability Based on Single-Port-Change Delay Fault Testing for Data Paths Yuki YOSHIKAWA, Satoshi OHTAKE, Michiko INOUE, Hideo FUJIWARA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a non-scan design-for-testability(DFT) method based on single-port-change(SPC) delay fault testing for register-transfer level data paths. SPC two-pattern testability guarantees detection of robust and non-robust testable path delay faults. SPC two-pattern tests for combinational logic blocks can be generated by using a combinational test generation algorithm with constraints. Comparing to arbitrary two-pattern tests, it is easier to generate control paths for SPC two-pattern tests. As a result, proposed method can reduce hardware overhead compared to the previos DFT method for hirarchical two-pattern testability. Furthermore, in order to relax overtesting, we propose a method to find subset of sequentially redundant paths. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | path delay fault / hierarchical test generaiotn / non-scan DFT / single-port-change two-pattern test |
| Paper # | VLD2004-73,ICD2004-159,DC2004-59 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2004/11/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design for Testability Based on Single-Port-Change Delay Fault Testing for Data Paths |
| Sub Title (in English) | |
| Keyword(1) | path delay fault |
| Keyword(2) | hierarchical test generaiotn |
| Keyword(3) | non-scan DFT |
| Keyword(4) | single-port-change two-pattern test |
| 1st Author's Name | Yuki YOSHIKAWA |
| 1st Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology() |
| 2nd Author's Name | Satoshi OHTAKE |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| 3rd Author's Name | Michiko INOUE |
| 3rd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| 4th Author's Name | Hideo FUJIWARA |
| 4th Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| Date | 2004/11/25 |
| Paper # | VLD2004-73,ICD2004-159,DC2004-59 |
| Volume (vol) | vol.104 |
| Number (no) | 480 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |