| Presentation | 2004/11/25 A method of DFT for data paths using bit-match function Yuu MURATA, Satoshi OHTAKE, Hideo FUJIWARA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a method of design-for-testability(DFT) which guarantees complete fault efficiency for register-transfer level data paths with irregular bit width. The proposed DFT method is an extension of the orthogonal scan method which was proposed for data paths with even bit width. The proposed method employs a combinational automatic test pattern generation(ATPG) tool. From the experimental results, the hardware overhead of the proposed method is smaller than that of full scan design which is a typical technique and allows combinational ATPG. The test application time of the proposed method is also shorter than that of full scan design. Moreover, the bit-match function proposed in this paper makes a method based on hierarchical testing for data paths with even bit width applicable to data paths with irregullar bit width. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Register-transfer level / design for testability / data paths with irregular bit-width / bit-match function / complete fault efficiency |
| Paper # | VLD2004-72,ICD2004-158,DC2004-58 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2004/11/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A method of DFT for data paths using bit-match function |
| Sub Title (in English) | |
| Keyword(1) | Register-transfer level |
| Keyword(2) | design for testability |
| Keyword(3) | data paths with irregular bit-width |
| Keyword(4) | bit-match function |
| Keyword(5) | complete fault efficiency |
| 1st Author's Name | Yuu MURATA |
| 1st Author's Affiliation | Nara Institute of Science and Technology() |
| 2nd Author's Name | Satoshi OHTAKE |
| 2nd Author's Affiliation | Nara Institute of Science and Technology |
| 3rd Author's Name | Hideo FUJIWARA |
| 3rd Author's Affiliation | Nara Institute of Science and Technology |
| Date | 2004/11/25 |
| Paper # | VLD2004-72,ICD2004-158,DC2004-58 |
| Volume (vol) | vol.104 |
| Number (no) | 480 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |