Presentation 2004/11/25
Efficient Generation of Instruction Templates for Pipeline Processor Self-Test
Shinya YOKOYAMA, Kazuko KAMBE, Michiko INOUE, Hideo FUJIWARA,
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Abstract(in English) Nowadays, pipeline processors are getting mainstream as processor structure. As testing methodology of such large-scale and high-speed processors, instruction-based self-test is getting much attention. As this methodology tests a processor by executing instructions of the processor, it has advantages of not causing hardware or delay overhead. In this paper, we propose an efficient generation methodology of instruction templates that are effective in test program generation for pipeline processor. Our method generates instruction templates paying attention to characteristic structure and behavior of pipeline processor. High-quality test is guaranteed by generating test program based on our instruction templates.
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Keyword(in English) Pipeline Processor / Self-Testing / Instruction Templates / Test Program / Hierarchical Test Generation
Paper # VLD2004-71,ICD2004-157,DC2004-57
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Conference Date 2004/11/25(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Efficient Generation of Instruction Templates for Pipeline Processor Self-Test
Sub Title (in English)
Keyword(1) Pipeline Processor
Keyword(2) Self-Testing
Keyword(3) Instruction Templates
Keyword(4) Test Program
Keyword(5) Hierarchical Test Generation
1st Author's Name Shinya YOKOYAMA
1st Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology()
2nd Author's Name Kazuko KAMBE
2nd Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology
3rd Author's Name Michiko INOUE
3rd Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology
4th Author's Name Hideo FUJIWARA
4th Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology
Date 2004/11/25
Paper # VLD2004-71,ICD2004-157,DC2004-57
Volume (vol) vol.104
Number (no) 480
Page pp.pp.-
#Pages 6
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