Presentation | 2004/11/25 Three Dimensional Module Packing using 3DBSG structure Hirokazu YAMAGISHI, Hiroshi NINOMIYA, Hideki ASAI, |
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Abstract(in English) | A three-dimensional (3D) chip design strategy will be of increasing significance in association with miniaturization of VLSI circuits. In the design of 3D VLSI, the placement which is to locate given 3D rectangular objects without overlapping each other in the 3D space, becomes an important issue. The 3D placement under the nonoverlapping constraint is called the 3D packing in which minimizing the volume of the package is required. This paper introduces a new coding system to encode the topology of 3D packing as an extension of BSG (Bounded-Sliceline Grid) for 2D packing. The novel coding system is referred to as three dimensional Bomided-Sliceplane Grid (3DBSG). The topology is a set of relative relations assigned to pairs of 3D modules such that "right-of" , "rear-of' and "above". We further show idea to handle L-shaped modules on the 3DBSG. The simulation results in which a standard simulated simulated annealing is utilized as an optimization algorithm, are demonstrated in order to test the validity of our 3D packing method based on 3DBSG. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | 3D Packing / 3DBSG / L-shaped modules / simulated annealing |
Paper # | VLD2004-65,ICD2004-151,DC2004-51 |
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Committee | ICD |
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Conference Date | 2004/11/25(1days) |
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Registration To | Integrated Circuits and Devices (ICD) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Three Dimensional Module Packing using 3DBSG structure |
Sub Title (in English) | |
Keyword(1) | 3D Packing |
Keyword(2) | 3DBSG |
Keyword(3) | L-shaped modules |
Keyword(4) | simulated annealing |
1st Author's Name | Hirokazu YAMAGISHI |
1st Author's Affiliation | Department of Systems Engineering, Shizuoka University() |
2nd Author's Name | Hiroshi NINOMIYA |
2nd Author's Affiliation | Department of Information Science, Shonan Institute of Technology |
3rd Author's Name | Hideki ASAI |
3rd Author's Affiliation | Department of Systems Engineering, Shizuoka University |
Date | 2004/11/25 |
Paper # | VLD2004-65,ICD2004-151,DC2004-51 |
Volume (vol) | vol.104 |
Number (no) | 480 |
Page | pp.pp.- |
#Pages | 6 |
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