Presentation | 2004/11/25 Accurate Pre-layout Estimation of Intra-cell Parasitics Using Fast Transistor-level Placement Hiroaki YOSHIDA, Kaushik DE, Vamsi BOPPANA, Makoto IKEDA, Kunihiro ASADA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Recently we proposed a pre-layout estimation method of intra-cell parasitics based on topology analysis. Although the paper showed that the parasitics inside simple cells could be estimated very accurately, it performs a poor estimation on complex cells. Additionally, even for such simple cells, it requires a deliberate calibration to obtain accurate estimates. To overcome these drawbacks, this paper proposes a new estimation method based on a fast transistor-level placement algorithm. Our experiment on an industrial standard cell library demonstrates the validity of the new method. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Standark cells / intra-cell parasitic estimation / transistor placement / transistor-level optimization |
Paper # | VLD2004-62,ICD2004-148,DC2004-48 |
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Committee | ICD |
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Conference Date | 2004/11/25(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Accurate Pre-layout Estimation of Intra-cell Parasitics Using Fast Transistor-level Placement |
Sub Title (in English) | |
Keyword(1) | Standark cells |
Keyword(2) | intra-cell parasitic estimation |
Keyword(3) | transistor placement |
Keyword(4) | transistor-level optimization |
1st Author's Name | Hiroaki YOSHIDA |
1st Author's Affiliation | Department of Electronic Engineering, University of Tokyo() |
2nd Author's Name | Kaushik DE |
2nd Author's Affiliation | Zenasis Technologies, Inc. |
3rd Author's Name | Vamsi BOPPANA |
3rd Author's Affiliation | Zenasis Technologies, Inc. |
4th Author's Name | Makoto IKEDA |
4th Author's Affiliation | VLSI Design and Education Center(VDEC), University of Tokyo |
5th Author's Name | Kunihiro ASADA |
5th Author's Affiliation | VLSI Design and Education Center(VDEC), University of Tokyo |
Date | 2004/11/25 |
Paper # | VLD2004-62,ICD2004-148,DC2004-48 |
Volume (vol) | vol.104 |
Number (no) | 480 |
Page | pp.pp.- |
#Pages | 6 |
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