| Presentation | 2004/11/25 Hierarchical Layout Synthesis for CMOS Logic Cells via Boolean Satisfiability Tetsuya IIZUKA, Makoto IKEDA, Kunihiro ASADA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a hierarchical layout synthesis method for high-speed layout synthesis of CMOS logic cells. The proposed method partitions a given transistor-level netlist into blocks and place all transistors hierarchically. Intra-block placement uses ail exact transistor placement method which is based on Boolean Satisfiability. In this step, a new cost function is introduced to maximize the number of the connections by diffusion sharing between blocks. All blocks are placed in the minimum area and the routability of a generated placement is checked using Boolean Satisfiability. The proposed method reduces the runtime for cell synthesis drastically. Although this method has possibility to generate wider placements than the exact minimum width placement generated flatly, the experimental results show that the width becomes larger for only 1 out of 32 cells. The comparison results between a commercial tool show that although the width of the layouts generated by our method is a little larger, the proposed method generates 32 CMOS logic cells in only 3% runtime. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | CMOS logic cell / high-speed layout synthesis / circuit partitioning / Boolean Satisfiability |
| Paper # | VLD2004-61,ICD2004-147,DC2004-47 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2004/11/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hierarchical Layout Synthesis for CMOS Logic Cells via Boolean Satisfiability |
| Sub Title (in English) | |
| Keyword(1) | CMOS logic cell |
| Keyword(2) | high-speed layout synthesis |
| Keyword(3) | circuit partitioning |
| Keyword(4) | Boolean Satisfiability |
| 1st Author's Name | Tetsuya IIZUKA |
| 1st Author's Affiliation | Dept. of Electronic Engineering, University of Tokyo() |
| 2nd Author's Name | Makoto IKEDA |
| 2nd Author's Affiliation | Dept. of Electronic Engineering, University of Tokyo:VLSI Design and Education Center (VDEC), University of Tokyo |
| 3rd Author's Name | Kunihiro ASADA |
| 3rd Author's Affiliation | Dept. of Electronic Engineering, University of Tokyo:VLSI Design and Education Center (VDEC), University of Tokyo |
| Date | 2004/11/25 |
| Paper # | VLD2004-61,ICD2004-147,DC2004-47 |
| Volume (vol) | vol.104 |
| Number (no) | 480 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |