| Presentation | 2004-10-22 Design of Cell Assignment Circuit for Dynamic Reconstruction Yutaka Koseki, Akinori Kanasugi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes the cell assignment algorithm for dynamic reconstruction, the design by VHDL, and the verification by simulation. Moreover, the circuit scale and the operation of speed are investigated. The target is an array system which consists of repetitions of the same cell. In the example which reconstructs 88 cell, the circuit scales is about 33,000 gates and the reconstruction time is about 12.9μs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Dynamic Reconstruction / Fault Tolerance / Array Processor |
| Paper # | SIP2004-102,ICD2004-134,IE2004-78 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2004/10/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of Cell Assignment Circuit for Dynamic Reconstruction |
| Sub Title (in English) | |
| Keyword(1) | Dynamic Reconstruction |
| Keyword(2) | Fault Tolerance |
| Keyword(3) | Array Processor |
| 1st Author's Name | Yutaka Koseki |
| 1st Author's Affiliation | Department of Electronic Engineering, Tokyo Denki University() |
| 2nd Author's Name | Akinori Kanasugi |
| 2nd Author's Affiliation | Department of Electronic Engineering, Tokyo Denki University |
| Date | 2004-10-22 |
| Paper # | SIP2004-102,ICD2004-134,IE2004-78 |
| Volume (vol) | vol.104 |
| Number (no) | 366 |
| Page | pp.pp.- |
| #Pages | 6 |
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