| Presentation | 2004-10-22 Bus architecture optimization method for IP-based design Kyoko UEDA, Keishi SAKANUSHI, Noboru YONEOKA, Yoshinori TAKEUCHI, Masaharu IMAI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In IP-based design, to find the optimal bus architecture is very important problem because bus architecture strongly affects the performance of the target system. This paper proposes a bus architecture optimization method using fast performance estimation. The optimization problem of bus architecture that is parameterized by bus topology, bus data transfer rate, bus bit width, and the number of buffers, is formalized and its exploration method is proposed. Proposed method explores all possible bus parameter sets estimating the performance and hardware area with profiling information. Experimental results show that proposed method can determine the optimal bus architecture and its time is drastically reduced compared to the conventional method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | IP-based design / bus architecture / performance estimation / branch-and-bound method |
| Paper # | SIP2004-101,ICD2004-133,IE2004-77 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 2004/10/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Bus architecture optimization method for IP-based design |
| Sub Title (in English) | |
| Keyword(1) | IP-based design |
| Keyword(2) | bus architecture |
| Keyword(3) | performance estimation |
| Keyword(4) | branch-and-bound method |
| 1st Author's Name | Kyoko UEDA |
| 1st Author's Affiliation | Graduate School of Information Science and Technology, Osaka University() |
| 2nd Author's Name | Keishi SAKANUSHI |
| 2nd Author's Affiliation | Graduate School of Information Science and Technology, Osaka University |
| 3rd Author's Name | Noboru YONEOKA |
| 3rd Author's Affiliation | Graduate School of Information Science and Technology, Osaka University |
| 4th Author's Name | Yoshinori TAKEUCHI |
| 4th Author's Affiliation | Graduate School of Information Science and Technology, Osaka University |
| 5th Author's Name | Masaharu IMAI |
| 5th Author's Affiliation | Graduate School of Information Science and Technology, Osaka University |
| Date | 2004-10-22 |
| Paper # | SIP2004-101,ICD2004-133,IE2004-77 |
| Volume (vol) | vol.104 |
| Number (no) | 366 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |