Presentation 2004-10-22
Small-Code-Size and Low-Latency Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications
Yasuo SUGURE, Seiji TAKEUCHI, Yuichi ABE, Hiromichi YAMADA, Kazuya HIRAYANAGI, Akihiko TOMITA, Kesami HAGIWARA, Takashi KATAOKA, Takanori SHIMURA,
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Abstract(in English) A 32-bit embedded RISC microcontroller core targeted for automotive, industrial, and PC-peripheral applications has been developed to offer the smaller code size, lower-latency instruction and interrupt processing. The core achieved 360MIPS and 400MFLOPS at 200MHz measured using Dhrystone 1.1. For smaller code size, new instructions have been added to the instruction set. These new instructions, as well as an enhanced C compiler, produce object files about 25% smaller than those for a previous designed core. A dual-issue superscalar structure consisting of three- or five-stage pipelines provides instruction processing with low latency. The cycle performance is an average of 1.8 times faster than the previous designed core. The superscalar structure and the register bank are used to save CPU registers to the resister bank in parallel when executing interrupt processing. This structure significantly improves interrupt response time from 37 cycles to 6 cycles.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Microcontroller / RISC / Smaller code size / Low-latency / Interrupt response time
Paper # SIP2004-93,ICD2004-125,IE2004-69
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Committee ICD
Conference Date 2004/10/15(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Small-Code-Size and Low-Latency Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications
Sub Title (in English)
Keyword(1) Microcontroller
Keyword(2) RISC
Keyword(3) Smaller code size
Keyword(4) Low-latency
Keyword(5) Interrupt response time
1st Author's Name Yasuo SUGURE
1st Author's Affiliation Central Research Laboratory, Hitachi Ltd.()
2nd Author's Name Seiji TAKEUCHI
2nd Author's Affiliation Renesas Technology Corp.
3rd Author's Name Yuichi ABE
3rd Author's Affiliation Hitachi Research Laboratory, Hitachi Ltd.
4th Author's Name Hiromichi YAMADA
4th Author's Affiliation Hitachi Research Laboratory, Hitachi Ltd.
5th Author's Name Kazuya HIRAYANAGI
5th Author's Affiliation Renesas Technology Corp.
6th Author's Name Akihiko TOMITA
6th Author's Affiliation Renesas Technology Corp.
7th Author's Name Kesami HAGIWARA
7th Author's Affiliation Renesas Technology Corp.
8th Author's Name Takashi KATAOKA
8th Author's Affiliation Renesas Technology Corp.
9th Author's Name Takanori SHIMURA
9th Author's Affiliation Central Research Laboratory, Hitachi Ltd.
Date 2004-10-22
Paper # SIP2004-93,ICD2004-125,IE2004-69
Volume (vol) vol.104
Number (no) 366
Page pp.pp.-
#Pages 6
Date of Issue