Presentation 2005/3/4
A study for High Density MRAM vehicled on 0.18μm MRAM
Hajime YAMAGISHI, Mitsuharu SHOJI, Ikuhiro YAMAMURA, Wataru OHTSUKA, Hiroyuki YAMADA, Motoaki NAKAMURA, Makoto MOTOYOSHI, Hiroshi KANO, Masanori HOSOMI, Tetsuya YAMAMOTO, Kazuhiro BESSYO, Hiroaki NARISAWA, Hideo HACHINO, Tsutomu SAGARA, Hironobu MORI, Chieko FUKUMOTO,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) In this paper, we have developed RIE technique for MTJ, self align process for shrinking of cell size, clad wiring for decreasing a programming current. And we study to reduce the switching dispersion and improve 0/1 separation of Magnetic Tunnel Junction (MTJ) elements in order to realize high density MRAM. In study of the relation between MTJ shapes and switching distribution, we found the switching dispersion correlate with MTJ shape and the "Saturn" shaped MTJ has best switching behavior. As regards the reading characteristics, the combination of the optimized MTJ pattern and process makes 21.4 sigma separation between high and low resistance states. Also the toggle mode MRAM (Savtchenko switching mode) [1] is evaluated and its effectiveness for high speed programming is confirmed.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) MRAM / MTJ / switching characteristic / Self-Align-Process / MTJ shape / Toggle mode MRAM
Paper # SDM2004-250
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Committee SDM
Conference Date 2005/3/4(1days)
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Paper Information
Registration To Silicon Device and Materials (SDM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A study for High Density MRAM vehicled on 0.18μm MRAM
Sub Title (in English)
Keyword(1) MRAM
Keyword(2) MTJ
Keyword(3) switching characteristic
Keyword(4) Self-Align-Process
Keyword(5) MTJ shape
Keyword(6) Toggle mode MRAM
1st Author's Name Hajime YAMAGISHI
1st Author's Affiliation Semiconductor Technology Development Group, Semiconductor Network Company, Sony Corporation()
2nd Author's Name Mitsuharu SHOJI
2nd Author's Affiliation Semiconductor Technology Development Group, Semiconductor Network Company, Sony Corporation
3rd Author's Name Ikuhiro YAMAMURA
3rd Author's Affiliation Semiconductor Technology Development Group, Semiconductor Network Company, Sony Corporation
4th Author's Name Wataru OHTSUKA
4th Author's Affiliation Semiconductor Technology Development Group, Semiconductor Network Company, Sony Corporation
5th Author's Name Hiroyuki YAMADA
5th Author's Affiliation Semiconductor Technology Development Group, Semiconductor Network Company, Sony Corporation
6th Author's Name Motoaki NAKAMURA
6th Author's Affiliation Semiconductor Technology Development Group, Semiconductor Network Company, Sony Corporation
7th Author's Name Makoto MOTOYOSHI
7th Author's Affiliation Semiconductor Technology Development Group, Semiconductor Network Company, Sony Corporation
8th Author's Name Hiroshi KANO
8th Author's Affiliation Information Technologies Laboratories, Sony Corporation
9th Author's Name Masanori HOSOMI
9th Author's Affiliation Information Technologies Laboratories, Sony Corporation
10th Author's Name Tetsuya YAMAMOTO
10th Author's Affiliation Information Technologies Laboratories, Sony Corporation
11th Author's Name Kazuhiro BESSYO
11th Author's Affiliation Information Technologies Laboratories, Sony Corporation
12th Author's Name Hiroaki NARISAWA
12th Author's Affiliation Information Technologies Laboratories, Sony Corporation
13th Author's Name Hideo HACHINO
13th Author's Affiliation LSI Design Division, Sony Corporation
14th Author's Name Tsutomu SAGARA
14th Author's Affiliation LSI Design Division, Sony Corporation
15th Author's Name Hironobu MORI
15th Author's Affiliation LSI Design Division, Sony Corporation
16th Author's Name Chieko FUKUMOTO
16th Author's Affiliation LSI Design Division, Sony Corporation
Date 2005/3/4
Paper # SDM2004-250
Volume (vol) vol.104
Number (no) 713
Page pp.pp.-
#Pages 6
Date of Issue