Presentation 2005/1/24
Challenge of low-k materials for 130, 90, 65nm node interconnect technology and beyond
H. Miyajima, K. Watanabe, K. Fujita, S. Ito, K. Tabuchi, T. Shimayama, K. Akiyama, T. Hachiya, K. Higashi, N. Nakamura, A. Kajita, N. Matsunaga, Y. Enomoto, R. Kanamura, M. Inohara, K. Honda, H. Kamijo, R. Nakata, H. Yano, N. Hayasaka, T. Hasegawa, S. Kadomura, H. Shibata, T. Yoda,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) In order to realize highly reliable low-k / Cu interconnects, optimum BEOL structures were developed for 130, 90 and 65 node logic devices respectively. For 65nm node BEOL structure, the conventional monolithic dual damascene (DD) structure was replaced by the hybrid-DD structure with PAr / SiOC stack films. It shows high extendibility to the next generation using newly developed technologies, such as eBeam cure and damage restoration techniques.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) low-k / ILD / BEOL / dual damascene / hybrid
Paper # SDM2004-247
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Conference Information
Committee SDM
Conference Date 2005/1/24(1days)
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Paper Information
Registration To Silicon Device and Materials (SDM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Challenge of low-k materials for 130, 90, 65nm node interconnect technology and beyond
Sub Title (in English)
Keyword(1) low-k
Keyword(2) ILD
Keyword(3) BEOL
Keyword(4) dual damascene
Keyword(5) hybrid
1st Author's Name H. Miyajima
1st Author's Affiliation Semiconductor Company, Toshiba Corporation()
2nd Author's Name K. Watanabe
2nd Author's Affiliation Semiconductor Company, Toshiba Corporation
3rd Author's Name K. Fujita
3rd Author's Affiliation Semiconductor Company, Toshiba Corporation
4th Author's Name S. Ito
4th Author's Affiliation Semiconductor Company, Toshiba Corporation
5th Author's Name K. Tabuchi
5th Author's Affiliation Semiconductor Solutions Network Company, Sony Corporation
6th Author's Name T. Shimayama
6th Author's Affiliation Semiconductor Solutions Network Company, Sony Corporation
7th Author's Name K. Akiyama
7th Author's Affiliation Semiconductor Company, Toshiba Corporation
8th Author's Name T. Hachiya
8th Author's Affiliation Semiconductor Company, Toshiba Corporation
9th Author's Name K. Higashi
9th Author's Affiliation Semiconductor Company, Toshiba Corporation
10th Author's Name N. Nakamura
10th Author's Affiliation Semiconductor Company, Toshiba Corporation
11th Author's Name A. Kajita
11th Author's Affiliation Semiconductor Company, Toshiba Corporation
12th Author's Name N. Matsunaga
12th Author's Affiliation Semiconductor Company, Toshiba Corporation
13th Author's Name Y. Enomoto
13th Author's Affiliation Semiconductor Solutions Network Company, Sony Corporation
14th Author's Name R. Kanamura
14th Author's Affiliation Semiconductor Solutions Network Company, Sony Corporation
15th Author's Name M. Inohara
15th Author's Affiliation Semiconductor Company, Toshiba Corporation
16th Author's Name K. Honda
16th Author's Affiliation Semiconductor Company, Toshiba Corporation
17th Author's Name H. Kamijo
17th Author's Affiliation Semiconductor Company, Toshiba Corporation
18th Author's Name R. Nakata
18th Author's Affiliation Semiconductor Company, Toshiba Corporation
19th Author's Name H. Yano
19th Author's Affiliation Semiconductor Company, Toshiba Corporation
20th Author's Name N. Hayasaka
20th Author's Affiliation Semiconductor Company, Toshiba Corporation
21th Author's Name T. Hasegawa
21th Author's Affiliation Semiconductor Solutions Network Company, Sony Corporation
22th Author's Name S. Kadomura
22th Author's Affiliation Semiconductor Solutions Network Company, Sony Corporation
23th Author's Name H. Shibata
23th Author's Affiliation Semiconductor Company, Toshiba Corporation
24th Author's Name T. Yoda
24th Author's Affiliation Semiconductor Company, Toshiba Corporation
Date 2005/1/24
Paper # SDM2004-247
Volume (vol) vol.104
Number (no) 645
Page pp.pp.-
#Pages 4
Date of Issue