Presentation | 2005/1/24 Thermally Robust Cu Interconnects with Cu-Ag alloy for Sub 45nm Node A. Isobayashi, Y. Enomoto, H. Yamada, S. Takahashi, S. Kadomura, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Cu interconnects reliability has been drastically improved by the introduction of Ag doped Cu (Cu-Ag) alloy seed. The usage of Cu-Ag remarkably suppressed stress induced voiding (SiV) in the lower wide metal which appeared by the additional anneal to prevent the degradation of the barrier metal. It has been explained by the Cu extrusion model where the void formation was caused by the poor adhesion between the upper barrier metal and the extruded lower metal under the via. The thermal stress hysteresis curve of Cu-Ag which shows the shift of the softening temperature higher suggests more thermal resistance to Cu extrusion than pure Cu. Also no degradation of interconnects performance and the minimum increase of the resistance were verified. These indicate that Cu-Ag alloy is the most feasible candidate for the improvement of the reliability issues of Cu interconnects with porous low-k film for 45nm node and beyond. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Cu interconnect / seed / reliability / Cu-Ag alloy / SiV / Cu extrusion / softening temperature |
Paper # | SDM2004-241 |
Date of Issue |
Conference Information | |
Committee | SDM |
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Conference Date | 2005/1/24(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Silicon Device and Materials (SDM) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Thermally Robust Cu Interconnects with Cu-Ag alloy for Sub 45nm Node |
Sub Title (in English) | |
Keyword(1) | Cu interconnect |
Keyword(2) | seed |
Keyword(3) | reliability |
Keyword(4) | Cu-Ag alloy |
Keyword(5) | SiV |
Keyword(6) | Cu extrusion |
Keyword(7) | softening temperature |
1st Author's Name | A. Isobayashi |
1st Author's Affiliation | Semiconductor Technology Development Group, Semiconductor Solutions Network Company, Sony Corporation() |
2nd Author's Name | Y. Enomoto |
2nd Author's Affiliation | Semiconductor Technology Development Group, Semiconductor Solutions Network Company, Sony Corporation |
3rd Author's Name | H. Yamada |
3rd Author's Affiliation | Technology Section 1, Device Development Department 2, Sony Semiconductor Kyushu Corporation |
4th Author's Name | S. Takahashi |
4th Author's Affiliation | Semiconductor Technology Development Group, Semiconductor Solutions Network Company, Sony Corporation |
5th Author's Name | S. Kadomura |
5th Author's Affiliation | Semiconductor Technology Development Group, Semiconductor Solutions Network Company, Sony Corporation |
Date | 2005/1/24 |
Paper # | SDM2004-241 |
Volume (vol) | vol.104 |
Number (no) | 645 |
Page | pp.pp.- |
#Pages | 5 |
Date of Issue |