| Presentation | 2005/1/24 Highly Reliable PVD/ALD/PVD Stacked Barrier Metal Structure for 45nm-Node Copper Dual-Damascene Interconnects Kazuyuki HIGASHI, Hitomi YAMAGUCHI, Seiichi OMOTO, Atsuko SAKATA, Tomio KATATA, Noriaki MATSUNAGA, Hideki SHIBATA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we describe highly reliable barrier metal structure for 45nm-node (140nm pitch) high performance copper interconnects. Issues and solutions for utilizing TaN barrier metal by atomic-layer deposition (ALD) process, which is the key technology for scaling down the barrier metal thickness, on low-k ILD materials were investigated. PVD/ALD/PVD stacked barrier metal structure was proposed from the viewpoint of factors affecting reliability such as stress-induced voiding (SiV) and electromigration (EM) endurance, and realized lower wiring resistance than that is attainable with the conventional process. We distinguished the role of each PVD film, and suggest the optimal barrier metal structure to realize highly reliable Cu dual-damascene interconnects. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Interconnects / Cu / ALD / Barrier metal / Reliability |
| Paper # | SDM2004-240 |
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| Committee | SDM |
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| Conference Date | 2005/1/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Highly Reliable PVD/ALD/PVD Stacked Barrier Metal Structure for 45nm-Node Copper Dual-Damascene Interconnects |
| Sub Title (in English) | |
| Keyword(1) | Interconnects |
| Keyword(2) | Cu |
| Keyword(3) | ALD |
| Keyword(4) | Barrier metal |
| Keyword(5) | Reliability |
| 1st Author's Name | Kazuyuki HIGASHI |
| 1st Author's Affiliation | System LSI Research & Development Center, Semiconductor Company, Toshiba Corporation() |
| 2nd Author's Name | Hitomi YAMAGUCHI |
| 2nd Author's Affiliation | System LSI Research & Development Center, Semiconductor Company, Toshiba Corporation |
| 3rd Author's Name | Seiichi OMOTO |
| 3rd Author's Affiliation | Process & Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation |
| 4th Author's Name | Atsuko SAKATA |
| 4th Author's Affiliation | Process & Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation |
| 5th Author's Name | Tomio KATATA |
| 5th Author's Affiliation | Process & Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation |
| 6th Author's Name | Noriaki MATSUNAGA |
| 6th Author's Affiliation | System LSI Research & Development Center, Semiconductor Company, Toshiba Corporation |
| 7th Author's Name | Hideki SHIBATA |
| 7th Author's Affiliation | System LSI Research & Development Center, Semiconductor Company, Toshiba Corporation |
| Date | 2005/1/24 |
| Paper # | SDM2004-240 |
| Volume (vol) | vol.104 |
| Number (no) | 645 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |