Presentation 2005/3/11
Control Signal Skew Scheduling for RT Level Datapaths
Takayuki OBATA, Mineo KANEKO,
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Abstract(in English) To synthesize high performance VLSI systems, the importance of exploiting interconnection delay information at higher level design is recognized. To improve system performance further in terms of total computation time and/or robustness to delay variation, we are going to introduce appropriate delays which differentiate the arrival times of control signals to registers. A similar technique to the skew of flip-flop control has been proposed for sequential circuits, and significant effort has been devoted to so-called clock scheduling. There is a difference that, in general, clock signal in a sequential circuit is fed to each register every time, while register control signal in RT level datapath is fed to a register only in selected (i.e., scheduled) control steps. When we comprehend the behavior of a datapath with data flows instead of executions of operations, a multiplexer in a datapath behaves as a gate starting and stopping data flow. Introduction of the skew in the arrival times of control signals to multiplexers will contribute, as well as the one for registers, to improve system performance. In this paper, we propose optimization algorithm of skew for both registers and multiplexers in placed RT level datapath.
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Keyword(in English) datapath / timing skew / scheduling
Paper # CPSY2004-107
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Conference Information
Committee CPSY
Conference Date 2005/3/11(1days)
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Registration To Computer Systems (CPSY)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Control Signal Skew Scheduling for RT Level Datapaths
Sub Title (in English)
Keyword(1) datapath
Keyword(2) timing skew
Keyword(3) scheduling
1st Author's Name Takayuki OBATA
1st Author's Affiliation School of Information Science, Japan Advanced Institute of Science And Technology()
2nd Author's Name Mineo KANEKO
2nd Author's Affiliation School of Information Science, Japan Advanced Institute of Science And Technology
Date 2005/3/11
Paper # CPSY2004-107
Volume (vol) vol.104
Number (no) 738
Page pp.pp.-
#Pages 5
Date of Issue