| Presentation | 2005/3/10 An LSI Design Method with Simultaneous Processing of Floorplanning and High-Level Synthesis Masafumi Otsuka, Kazuhito Ito, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | With the recent advances in the semiconductor manufacturing technologies, the delay of communication on wires becomes dominant among the total delay. Therefore it is getting difficult to obtain high-speed LSIs by using the conventional LSI design methods. In this paper, to overcome the problem of the conventional design methods, we propose an LSI design method where floorplanning and high-level synthesis are performed simultaneously. This method consists of (1) functional-unit binding, (2) floorplanning the functional-units and registers, and (3) scheduling and register binding, and the best solution is searched by using simulated annealing. We show effectiveness of the proposed method through experiments. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | LSI design method / High-level synthesis / Floorplanning / Interconnect delay |
| Paper # | CPSY2004-94 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 2005/3/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An LSI Design Method with Simultaneous Processing of Floorplanning and High-Level Synthesis |
| Sub Title (in English) | |
| Keyword(1) | LSI design method |
| Keyword(2) | High-level synthesis |
| Keyword(3) | Floorplanning |
| Keyword(4) | Interconnect delay |
| 1st Author's Name | Masafumi Otsuka |
| 1st Author's Affiliation | Department of Electrical and Electronic Systems, Saitama University() |
| 2nd Author's Name | Kazuhito Ito |
| 2nd Author's Affiliation | Department of Electrical and Electronic Systems, Saitama University |
| Date | 2005/3/10 |
| Paper # | CPSY2004-94 |
| Volume (vol) | vol.104 |
| Number (no) | 737 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |