Presentation 2005-01-26
Design and Development of Microprocessors on a Hardware/Software Co-learning System
Koichiro NAKAMURA, Hoang Anh TUAN, Shigeru OYANAGI, Katsuhiro YAMAZAKI,
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Abstract(in English) The hardware/software co-learning system helps user to learn both hardware and software such as assembly programming, processor design and verification using FPGA boards by understanding processor architecture. This paper describes how to learn both hardware and software on this system. We have developed single cycle, multi cycle, pipeline and superscalar microprocessors based on a basic instruction set for this system. In addition, a single cycle microprocessor for another instruction set is described. At last we discuss about a support system for developing a processor which aims to efficiently debug both hardware and software.
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Keyword(in English) Hardware/Software Co-learning System / Microprocessor / Processor Architecture
Paper # VLD2004-116,CPSY2004-82
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Committee CPSY
Conference Date 2005/1/19(1days)
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Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design and Development of Microprocessors on a Hardware/Software Co-learning System
Sub Title (in English)
Keyword(1) Hardware/Software Co-learning System
Keyword(2) Microprocessor
Keyword(3) Processor Architecture
1st Author's Name Koichiro NAKAMURA
1st Author's Affiliation Graduate School of Science and Engineering, Ritsumeikan University()
2nd Author's Name Hoang Anh TUAN
2nd Author's Affiliation Graduate School of Science and Engineering, Ritsumeikan University
3rd Author's Name Shigeru OYANAGI
3rd Author's Affiliation Graduate School of Science and Engineering, Ritsumeikan University
4th Author's Name Katsuhiro YAMAZAKI
4th Author's Affiliation Graduate School of Science and Engineering, Ritsumeikan University
Date 2005-01-26
Paper # VLD2004-116,CPSY2004-82
Volume (vol) vol.104
Number (no) 592
Page pp.pp.-
#Pages 6
Date of Issue