| Presentation | 2004/11/25 Application of Reconfigurable Logics to Image Processing Teruo TAMAMA, Tomohiko SAITO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | An image processing board with two FPGAs, on which reconfiguration of one FPGA is controlled by the other, has been fabricated. A dedicated sequencer for it has been developed. With this board, three items of image processing, such as contrast enhancement, noise reduction, and outline abstraction, have been performed sequentially and successfully. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Reconfigurable Logic / Image Processing / FPGA / Contrast Enhancement / Outline Abstraction |
| Paper # | CPSY2004-48 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 2004/11/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Application of Reconfigurable Logics to Image Processing |
| Sub Title (in English) | |
| Keyword(1) | Reconfigurable Logic |
| Keyword(2) | Image Processing |
| Keyword(3) | FPGA |
| Keyword(4) | Contrast Enhancement |
| Keyword(5) | Outline Abstraction |
| 1st Author's Name | Teruo TAMAMA |
| 1st Author's Affiliation | Dept. Computer Science, Shizuoka Institute of Science & Technology() |
| 2nd Author's Name | Tomohiko SAITO |
| 2nd Author's Affiliation | Graduate School, Shizuoka Institute of Science & Technology |
| Date | 2004/11/25 |
| Paper # | CPSY2004-48 |
| Volume (vol) | vol.104 |
| Number (no) | 476 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |