| Presentation | 2005-06-28 Complementary Ferroelectric Capacitor Logic and its Application to Fully Parallel Arithmetic VLSI Shoun MATSUNAGA, Takahiro HANYU, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a Complementary Ferroelectric Capacitor Logic-in-Memory circuit that makes it possible easily to realize fully parallel structures with a quick-on function. The Complementary Ferroelectric Capacitor Logic-in-Memory circuit can realize fully parallel structures compactly without a overhead of storage circuits, because the realization of a logic function using a ferroelectric capacitor enables to merge a non-volatile storage function and a logic function compactly at the device level. Since the result of a logic operation is stored in the ferroelectric capacitor automatically, the voltage source can be done switching on-off at any time, furthermore a quick-on VLSI can be realize easily. As a typical fully parallel arithmetic VLSI using the proposesd circuit, a fine-grain pipelined adder is discussed, and its performance is compared with that of a corresponding CMOS implementation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | complementary ferroelectric capacitor logic / non-volatile storage / quick-on / fully parallel structure / fine-grain pipelining |
| Paper # | CAS2005-25,VLD2005-36,SIP2005-49 |
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| Conference Information | |
| Committee | CAS |
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| Conference Date | 2005/6/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Circuits and Systems (CAS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Complementary Ferroelectric Capacitor Logic and its Application to Fully Parallel Arithmetic VLSI |
| Sub Title (in English) | |
| Keyword(1) | complementary ferroelectric capacitor logic |
| Keyword(2) | non-volatile storage |
| Keyword(3) | quick-on |
| Keyword(4) | fully parallel structure |
| Keyword(5) | fine-grain pipelining |
| 1st Author's Name | Shoun MATSUNAGA |
| 1st Author's Affiliation | Research Institute of Electrical Communication, Tohoku University() |
| 2nd Author's Name | Takahiro HANYU |
| 2nd Author's Affiliation | Research Institute of Electrical Communication, Tohoku University |
| Date | 2005-06-28 |
| Paper # | CAS2005-25,VLD2005-36,SIP2005-49 |
| Volume (vol) | vol.105 |
| Number (no) | 146 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |