| Presentation | 2005-06-28 A Memory-Reduction Method for Partially-Parallel LDPC Decoder Based on Min-Sum Algorithm Tatsuyuki ISHIKAWA, Kazunori SHIMIZU, Takeshi IKENAGA, Satoshi GOTO, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a memory-reduction method for partially-parallel LDPC decoder based on min-sum algorithm. We focus on the reliability messages by the row-operation can be obtained from only two absolute value or three signed value. In our proposed LDPC decoder, the row-operation module outputs the minimum absolute value, second minimum value, the flag signals and the signed bits, and they are stored in memory of row-operation module. These values and signals are fed to column operation module. We implemented partially-parallel LDPC decoder based on our proposed method. Implementation result shows that memory requirement can be reduced by our implemented LDPC decoder. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | low-density parity check (LDPC) codes / min-sum algorithm / partially-parallel LDPC decoder / memory-reduction |
| Paper # | CAS2005-22,VLD2005-33,SIP2005-46 |
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| Conference Information | |
| Committee | CAS |
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| Conference Date | 2005/6/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Circuits and Systems (CAS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Memory-Reduction Method for Partially-Parallel LDPC Decoder Based on Min-Sum Algorithm |
| Sub Title (in English) | |
| Keyword(1) | low-density parity check (LDPC) codes |
| Keyword(2) | min-sum algorithm |
| Keyword(3) | partially-parallel LDPC decoder |
| Keyword(4) | memory-reduction |
| 1st Author's Name | Tatsuyuki ISHIKAWA |
| 1st Author's Affiliation | Graduate School of Information, Production and Systems, Waseda University() |
| 2nd Author's Name | Kazunori SHIMIZU |
| 2nd Author's Affiliation | Graduate School of Information, Production and Systems, Waseda University |
| 3rd Author's Name | Takeshi IKENAGA |
| 3rd Author's Affiliation | Graduate School of Information, Production and Systems, Waseda University |
| 4th Author's Name | Satoshi GOTO |
| 4th Author's Affiliation | Graduate School of Information, Production and Systems, Waseda University |
| Date | 2005-06-28 |
| Paper # | CAS2005-22,VLD2005-33,SIP2005-46 |
| Volume (vol) | vol.105 |
| Number (no) | 146 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |