Presentation 2005-06-28
Optimal Design of Fast Adders Based on Redundant Number Systems
Naofumi HOMMA, Takahumi AOKI, Tatsuo HIGUCHI,
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Abstract(in English) This paper presents a unified representation of fast addition algorithms called Counter Tree Diagrams (CTDs) and its application to the optimal design of redundant arithmetic adders. By using CTDs, we can obtain possible constant-time redundant adders in a systematic way without using specific knowledge about underlying addition algorithms. The potential of the proposed approach is demonstrated through an experimental design of the optimal RB adders. The result shows that the obtained RB adder achieves about 30-40% higher performance in terms of power-delay product compared with the conventional designs.
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Keyword(in English) arithmetic circuits / hardware algorithms / redundant number systems
Paper # CAS2005-20,VLD2005-31,SIP2005-44
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Committee CAS
Conference Date 2005/6/21(1days)
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Registration To Circuits and Systems (CAS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Optimal Design of Fast Adders Based on Redundant Number Systems
Sub Title (in English)
Keyword(1) arithmetic circuits
Keyword(2) hardware algorithms
Keyword(3) redundant number systems
1st Author's Name Naofumi HOMMA
1st Author's Affiliation Graduate School of Information Sciences Tohoku University()
2nd Author's Name Takahumi AOKI
2nd Author's Affiliation Graduate School of Information Sciences Tohoku University
3rd Author's Name Tatsuo HIGUCHI
3rd Author's Affiliation Department of Electronic Engineering, Faculty of Engineering, Tohoku Institute of Technology
Date 2005-06-28
Paper # CAS2005-20,VLD2005-31,SIP2005-44
Volume (vol) vol.105
Number (no) 146
Page pp.pp.-
#Pages 6
Date of Issue