Presentation 2005-01-21
Nonvolatile SRAM based on Phase Change
Masashi TAKATA, Kazuya NAKAYAMA, Takatomi IZUMI, KITAGAWA Akio /,
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Abstract(in English) We propose a novel architecture combining SRAM with PRAM (Phase Change nonvolatile RAM). This architecture (termed PNSRAM) adds nonvolatile to SRAM by incorporating 1T2R. As a result, this circuit gains release from stand-by power consumption and unlimited nonvolatile program cycle. This paper described about PNSRAM circuit designed with 0.18μm-CMOS process. It has been confirmed with a circuit simulation that the volatile and nonvolatile read/write operations work successfully. PNSRAM has the power consumption over volatile read/write operation as much as the conventional SRAM. The read operation is completed with 1.36nsec at 1.0V supply voltage.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Phase change / SRAM and OUM
Paper # CAS2004-80
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Committee CAS
Conference Date 2005/1/14(1days)
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Registration To Circuits and Systems (CAS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Nonvolatile SRAM based on Phase Change
Sub Title (in English)
Keyword(1) Phase change
Keyword(2) SRAM and OUM
1st Author's Name Masashi TAKATA
1st Author's Affiliation The authors are with the Faculty of Engineering, Kanazawa University()
2nd Author's Name Kazuya NAKAYAMA
2nd Author's Affiliation The author is with the School of Health Sciences, Kanazawa University
3rd Author's Name Takatomi IZUMI
3rd Author's Affiliation The authors are with the Faculty of Engineering, Kanazawa University
4th Author's Name KITAGAWA Akio /
4th Author's Affiliation The authors are with the Faculty of Engineering, Kanazawa University
Date 2005-01-21
Paper # CAS2004-80
Volume (vol) vol.104
Number (no) 557
Page pp.pp.-
#Pages 6
Date of Issue