Presentation 2004-11-04
Arithmetic Cost Reduction Algorithm for Linear Transformation Circuits Considering the Synthesis Order of Coefficient Set
Keisuke SATO, Takao SASAKI, Hisamichi TOYOSHIMA,
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Abstract(in English) For synthesis of linear transformation circuits, it is generally used that the coefficient matrix is partitioned into multiple constant multiplication (MCM) circuits and their outputs are added. The linear transform circuit can also be represented as an expansion of a single input and coefficient of the MCM circuit into multiple inputs and coefficients. With this representation, the linear transform circuit can be synthesized without the final additions. However, this synthesis method have a problem that arithmetic cost much depends on the synthesis order of coefficient sets. In this research, we propose a synthesis method of linear transformation circuits that can reduce arithmetic cost using a combinatorial optimization algorithm.
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Keyword(in English) Linear Transformation Circuits / Optimization Algorithm / Multiple Constant Multiplication / Arithmetic Cost
Paper # CAS2004-46,CST2004-25
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Committee CAS
Conference Date 2004/10/28(1days)
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Registration To Circuits and Systems (CAS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Arithmetic Cost Reduction Algorithm for Linear Transformation Circuits Considering the Synthesis Order of Coefficient Set
Sub Title (in English)
Keyword(1) Linear Transformation Circuits
Keyword(2) Optimization Algorithm
Keyword(3) Multiple Constant Multiplication
Keyword(4) Arithmetic Cost
1st Author's Name Keisuke SATO
1st Author's Affiliation Faculty of Engineering, Kanagawa University()
2nd Author's Name Takao SASAKI
2nd Author's Affiliation Faculty of Engineering, Kanagawa University
3rd Author's Name Hisamichi TOYOSHIMA
3rd Author's Affiliation Faculty of Engineering, Kanagawa University
Date 2004-11-04
Paper # CAS2004-46,CST2004-25
Volume (vol) vol.104
Number (no) 402
Page pp.pp.-
#Pages 4
Date of Issue