Presentation | 2004-10-15 High-Throughput and Low-Power Packet Processing Architecture for Next-Generation IP Backbone Router Michitaka OKUNO, Hiroaki NISHI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | The latest high-end IP backbone routers use packet-processing engines (PPEs), which can achieve about 20-Gbps(gigabit per second) throughput. The next-generation IP backbone routers around 2007 will require 100-Gbps throughput for those PPEs. However, it is difficult to use the extension architecture of a conventional PPE, which use many number of inner processing units for parallel packet processing. Because increasing the number of inner processing units leads issues of large die size and power consumption. In this paper, the details of a novel cache-based PPE which has a cache and special hardware are revealed. The cache-based PPE exploits the network traffic nature, i.e., packets, which have same header each other appear over a short time repeatedly. We were able to estimate that the cache-based PPE can achieve 100-Gbps packet-processing throughput with only 36.6% of the die size and 32.6% of the maximum power consumption required by the conventional PPE in the case of todays 0.13-um CMOS technology, 1.2-V core voltage, and 333-MHz frequency. Cache-based PPE can satisfy high throughput and low power consumption for the next-generation high-end routers. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | 100-gigabit Ethernet / Router, Low-Power Consumption / Packet-Processing Engine / Cache-based Packet-Processing Engine / Process-learning Cache |
Paper # | IN2004-89 |
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Committee | IN |
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Conference Date | 2004/10/8(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Information Networks (IN) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | High-Throughput and Low-Power Packet Processing Architecture for Next-Generation IP Backbone Router |
Sub Title (in English) | |
Keyword(1) | 100-gigabit Ethernet |
Keyword(2) | Router, Low-Power Consumption |
Keyword(3) | Packet-Processing Engine |
Keyword(4) | Cache-based Packet-Processing Engine |
Keyword(5) | Process-learning Cache |
1st Author's Name | Michitaka OKUNO |
1st Author's Affiliation | Central Research Laboratory, Hitachi, Ltd.() |
2nd Author's Name | Hiroaki NISHI |
2nd Author's Affiliation | Faculty of Science and Technology, Keio University |
Date | 2004-10-15 |
Paper # | IN2004-89 |
Volume (vol) | vol.104 |
Number (no) | 340 |
Page | pp.pp.- |
#Pages | 6 |
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