| Presentation | 2005/1/20 Implementation of Ultra-Low Power Nanoprocessors based on Hexagonal BDD Quantum Circuits Seiya KASAI, Miki YUMOTO, Takahiro TAMURA, Hideki HASEGAWA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Implementation of ultra-low power nanoprocessors (NPUs) based on hexagonal BDD quantum circuits are investigated. The circuits and systems are implemented utilizing hexagonal nanowire networks controlled by nano-Schottky gates, and they operate with a few electrons utilizing quantum transport for ultra-low power consumption. Based on this architecture, subsystems and elemental parts of digital signal processors including ALUs were designed and fabricated. The hexagonal BDD-based 2-bit NPUs were successfully designed and their correct operations were confirmed by circuit simulation. Power consumption and size of the NPUs were also discussed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Nanoprocessor / Binary Decision Diagram (BDD) / Quantum Nanodevice / Hexagonal Nanowire Network |
| Paper # | ED2004-232,SDM2004-227 |
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| Conference Information | |
| Committee | ED |
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| Conference Date | 2005/1/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of Ultra-Low Power Nanoprocessors based on Hexagonal BDD Quantum Circuits |
| Sub Title (in English) | |
| Keyword(1) | Nanoprocessor |
| Keyword(2) | Binary Decision Diagram (BDD) |
| Keyword(3) | Quantum Nanodevice |
| Keyword(4) | Hexagonal Nanowire Network |
| 1st Author's Name | Seiya KASAI |
| 1st Author's Affiliation | Graduate School of Information Science and Technology, and Research Center for Integrated Quantum Electronics, Hokkaido University() |
| 2nd Author's Name | Miki YUMOTO |
| 2nd Author's Affiliation | Graduate School of Information Science and Technology, and Research Center for Integrated Quantum Electronics, Hokkaido University |
| 3rd Author's Name | Takahiro TAMURA |
| 3rd Author's Affiliation | Graduate School of Information Science and Technology, and Research Center for Integrated Quantum Electronics, Hokkaido University |
| 4th Author's Name | Hideki HASEGAWA |
| 4th Author's Affiliation | Graduate School of Information Science and Technology, and Research Center for Integrated Quantum Electronics, Hokkaido University |
| Date | 2005/1/20 |
| Paper # | ED2004-232,SDM2004-227 |
| Volume (vol) | vol.104 |
| Number (no) | 622 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |