Presentation 2004/11/5
Reliability of 0.18 μm gate GaAs-MESFETs fabricated by i-line lithography process
Yasuhiro TOSAKA, Masataka WATANABE, Daiji FUKUSHI, Hiroshi YANO, Shigeru NAKAJIMA,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A 0.18 μm GaAs-MESFET fabrication process with low cost and high uniformity was established by means of i-line lithography and ion-implantation technology. As the result of the investigation of 0.18 μm GaAs-MESFET using the high temperature accelerated life test, the activation energy of 1.54eV and mean time to failure (MTTF) of 2.4×10^5 hours at a junction temperature of 150℃ ware obtained. The sinking of Ti metal at the interface between the gate metal and GaAs substrate was revealed using the analysis of TEM and EDX.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) MESFET / i-line lithography / reliability / activation energy / gate-sinking
Paper # R2004-46,ED2004-159
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Committee ED
Conference Date 2004/11/5(1days)
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Registration To Electron Devices (ED)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Reliability of 0.18 μm gate GaAs-MESFETs fabricated by i-line lithography process
Sub Title (in English)
Keyword(1) MESFET
Keyword(2) i-line lithography
Keyword(3) reliability
Keyword(4) activation energy
Keyword(5) gate-sinking
1st Author's Name Yasuhiro TOSAKA
1st Author's Affiliation Eudyna Devices Inc.()
2nd Author's Name Masataka WATANABE
2nd Author's Affiliation Eudyna Devices Inc.
3rd Author's Name Daiji FUKUSHI
3rd Author's Affiliation Eudyna Devices Inc.
4th Author's Name Hiroshi YANO
4th Author's Affiliation Eudyna Devices Inc.
5th Author's Name Shigeru NAKAJIMA
5th Author's Affiliation Eudyna Devices Inc.
Date 2004/11/5
Paper # R2004-46,ED2004-159
Volume (vol) vol.104
Number (no) 428
Page pp.pp.-
#Pages 6
Date of Issue