Presentation 2005-01-27
High-resolution failure analysis with SIL plate
Takeshi Yoshida, Tohru Koyama, Junko Komori, Yoji Masiko,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) We developped FOSSIL (Forming Si Substrate into SIL (Solid Immersion Lens)) technique that realized theoritical spatial resolution and detection performance as SIL by directly forming the Silicon in 2002. However there is restriction that a viewpoint is fixed with FOSSIL, this time, we developed SIL plate that enables to move viewpoint. SIL plate can be applied with wafer sample which is impossible for conventional SIL without changing equipment composition. About detection performance, we confiremed that spatial resolution of SIL plate less than that of FOSSIL, but SIL plate can realize transistor level analysis for devices of the 90nm node. This technique is promising as practical SIL technique that is easily applicable.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Emission analysis / OBIRCH analysis / SIL(Solid Immersion Lens) / Resolution
Paper # CPM2004-157,ICD2004-202
Date of Issue

Conference Information
Committee CPM
Conference Date 2005/1/20(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Component Parts and Materials (CPM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) High-resolution failure analysis with SIL plate
Sub Title (in English)
Keyword(1) Emission analysis
Keyword(2) OBIRCH analysis
Keyword(3) SIL(Solid Immersion Lens)
Keyword(4) Resolution
1st Author's Name Takeshi Yoshida
1st Author's Affiliation Process & Device Analysis Enginnering Development LSI Manufactureing Technology Unit, Renesas Technology()
2nd Author's Name Tohru Koyama
2nd Author's Affiliation Process & Device Analysis Enginnering Development LSI Manufactureing Technology Unit, Renesas Technology
3rd Author's Name Junko Komori
3rd Author's Affiliation Process & Device Analysis Enginnering Development LSI Manufactureing Technology Unit, Renesas Technology
4th Author's Name Yoji Masiko
4th Author's Affiliation Process & Device Analysis Enginnering Development LSI Manufactureing Technology Unit, Renesas Technology
Date 2005-01-27
Paper # CPM2004-157,ICD2004-202
Volume (vol) vol.104
Number (no) 626
Page pp.pp.-
#Pages 5
Date of Issue