| Presentation | 2004/11/4 Characteristic of Thin VN Barrier in Cu/VN/SiOC/Si System Mayumi B. TAKEYAMA, Genta MIZUNO, Yoshie WAKABAYASHI, Atsushi NOYA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As the Cu interconnect feature size decreases, the signal delay due to resistance-capacitance (RC) product becomes the major limitation to achieve faster circuit speeds. In order to reduce the RC time delays, an application of low dielectric constant materials (low-k) as a field insulating layer has examined. In the present study, the thin VN barrier with ～10 nm in thickness is examined as the barrier in the Cu/VN/SiOC/Si system with the low-k material. The system showed the excellent thermal stability after annealing at 500℃ higher for 30 min without structural change of the barrier and interfacial reaction in the system due to annealing. This is because the VN barrier has excellent properties in chemical stability and in structural stability. Moreover, the application of the VN barrier with low resistivity is also effective to reduce the RC delays, because the VN barrier is lower in resistivity than the Ta or TaN barrier. Therefore, the VN barrier can be applicable between the Cu interconnect and CVD-SiOC layer as the 65nm-node technology. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Si-ULSI / Cu interconnects / low-k / VN / diffusion barrier |
| Paper # | CPM2004-130 |
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| Conference Information | |
| Committee | CPM |
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| Conference Date | 2004/11/4(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Component Parts and Materials (CPM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Characteristic of Thin VN Barrier in Cu/VN/SiOC/Si System |
| Sub Title (in English) | |
| Keyword(1) | Si-ULSI |
| Keyword(2) | Cu interconnects |
| Keyword(3) | low-k |
| Keyword(4) | VN |
| Keyword(5) | diffusion barrier |
| 1st Author's Name | Mayumi B. TAKEYAMA |
| 1st Author's Affiliation | Dept. of Electrical and Electronic Engineering, Kitami Institute of Technology() |
| 2nd Author's Name | Genta MIZUNO |
| 2nd Author's Affiliation | Dept. of Electrical and Electronic Engineering, Kitami Institute of Technology |
| 3rd Author's Name | Yoshie WAKABAYASHI |
| 3rd Author's Affiliation | Dept. of Electrical and Electronic Engineering, Kitami Institute of Technology:(Present address)Forum Engineering Inc. |
| 4th Author's Name | Atsushi NOYA |
| 4th Author's Affiliation | Dept. of Electrical and Electronic Engineering, Kitami Institute of Technology |
| Date | 2004/11/4 |
| Paper # | CPM2004-130 |
| Volume (vol) | vol.104 |
| Number (no) | 425 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |