| Presentation | 2004-10-22 Consideration of Design Methodology of SFQ Logic Circuits Aya AKIMOTO, Yuki YAMANASHI, Nobuyuki YOSHIKAWA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recent progress in the SFQ logic circuit design methodology enables us to make large-scale SFQ circuits composed of several thousands of Josephson junctions. However, it is hard now to optimize a logic function because there are no logic synthesis tools for SFQ logic circuits. Our target is to introduce logic synthesis environment into our top-down design flow. In this paper we have considered how to perform logic synthesis by using logic synthesis tools existent for semiconductor circuits. Fundamental difference of the SFQ gate from the semiconductor gate in terms of logic synthesis is that almost SFQ gates are clocked gate, which means that the gates have to be clocked by SFQ pulses. In our approach, we divide the task into two stages; a logic synthesis stage and a clock distribution stage. To obtain higher throughput we improve the delay of a critical path by inserting a D flip-flop between clocked gates. Based on the proposed design approach, we designed a controller, which is a circuit component of a SFQ microprocessor " CORE1 β" and observed its correct operation with a simulation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SFQ logic circuit / design Methodology / logic Synthesis / clock Distribution |
| Paper # | SCE2004-28 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 2004/10/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Consideration of Design Methodology of SFQ Logic Circuits |
| Sub Title (in English) | |
| Keyword(1) | SFQ logic circuit |
| Keyword(2) | design Methodology |
| Keyword(3) | logic Synthesis |
| Keyword(4) | clock Distribution |
| 1st Author's Name | Aya AKIMOTO |
| 1st Author's Affiliation | Faculty of Engineering, Yokohama National University() |
| 2nd Author's Name | Yuki YAMANASHI |
| 2nd Author's Affiliation | Faculty of Engineering, Yokohama National University |
| 3rd Author's Name | Nobuyuki YOSHIKAWA |
| 3rd Author's Affiliation | Faculty of Engineering, Yokohama National University |
| Date | 2004-10-22 |
| Paper # | SCE2004-28 |
| Volume (vol) | vol.104 |
| Number (no) | 373 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |