| Presentation | 2004-10-22 Advanced Design Approaches for SFQ Logic Circuits based on the Binary Decision Diagram Takanobu Nishigai, Maki Ito, Nobuyuki Yoshikawa, Koji Obata, Kazuyoshi Takagi, Naofumi Takagi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have been developing a design methodology of SFQ logic circuits based on the binary decision diagram (BDD) . In the previously proposed BDD SFQ logic circuits, a one-to-two binary gate has been used as a node in a BDD tree. In this study we will propose new implementation methods of SFQ BDD circuits using new approaches, in which two nodes are implemented by a 2-input 2-output cell. By employing the new approach, we have designed and implemented a full adder using the NEC 2.5kA/cm^2 Nb standard process and the CONNECT cell library. The maximum operating frequency of the full adder was found to be 40 GHz by circuit simulation, and 32.8 GHz by on-chip high-speed tests. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | binary decision diagram / BDD / asynchronous circuit / dual rail / SFQ logic circuit |
| Paper # | SCE2004-27 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 2004/10/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Advanced Design Approaches for SFQ Logic Circuits based on the Binary Decision Diagram |
| Sub Title (in English) | |
| Keyword(1) | binary decision diagram |
| Keyword(2) | BDD |
| Keyword(3) | asynchronous circuit |
| Keyword(4) | dual rail |
| Keyword(5) | SFQ logic circuit |
| 1st Author's Name | Takanobu Nishigai |
| 1st Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University() |
| 2nd Author's Name | Maki Ito |
| 2nd Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 3rd Author's Name | Nobuyuki Yoshikawa |
| 3rd Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
| 4th Author's Name | Koji Obata |
| 4th Author's Affiliation | Department of Information Engineering, Nagoya University |
| 5th Author's Name | Kazuyoshi Takagi |
| 5th Author's Affiliation | Department of Information Engineering, Nagoya University |
| 6th Author's Name | Naofumi Takagi |
| 6th Author's Affiliation | Department of Information Engineering, Nagoya University |
| Date | 2004-10-22 |
| Paper # | SCE2004-27 |
| Volume (vol) | vol.104 |
| Number (no) | 373 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |