| Presentation | 2005/4/8 High-level asynchronous circuits synthesis under resource constraints Hiroomi ONDA, Atsushi MATSUMOTO, Tomohiro YONEDA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Designing asynchronous circuits requires special expertise. There are, however, few tools to support it. For synthesizing large and practical designs, it is essential to use high level specification languages. In this work, we have developed a methodology to synthesize asynchronous circuits from a high level specification language, which includes scheduling and allocation algorithms tuned for asynchronous circuits to satisfy resource constraints. In order to demonstrate the applicability of the proposed method, we have synthesized two circuits from the same specification, an asynchronous circuit by the proposed method and a synchronous circuit by an existing tool, and compared the performance of those two circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Asynchronous circuit / High level synthesis / SpecC / Balsa / DFG / Scheduling / Register shearing |
| Paper # | CPSY2005-5,DC2005-5 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2005/4/8(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High-level asynchronous circuits synthesis under resource constraints |
| Sub Title (in English) | |
| Keyword(1) | Asynchronous circuit |
| Keyword(2) | High level synthesis |
| Keyword(3) | SpecC |
| Keyword(4) | Balsa |
| Keyword(5) | DFG |
| Keyword(6) | Scheduling |
| Keyword(7) | Register shearing |
| 1st Author's Name | Hiroomi ONDA |
| 1st Author's Affiliation | Graduate School of Information Science and Engineering, Tokyo Institute of Technology() |
| 2nd Author's Name | Atsushi MATSUMOTO |
| 2nd Author's Affiliation | Graduate School of Information Science and Engineering, Tokyo Institute of Technology |
| 3rd Author's Name | Tomohiro YONEDA |
| 3rd Author's Affiliation | Infrastructure Systems Research Division, National Institute of Informatics |
| Date | 2005/4/8 |
| Paper # | CPSY2005-5,DC2005-5 |
| Volume (vol) | vol.105 |
| Number (no) | 4 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |