| Presentation | 2005/2/11 Interconnect Open Detection by Ramp Voltage Application Yukiya MIURA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have proposed a method for detecting interconnect open faults of CMOS combinational circuits by applying a ramp voltage to the power supply terminals. The method requires only one test vector to detect fault effect as a delay fault or an erroneous logic value at primary outputs. In this paper, we show feasibility of the proposed method by changing several circuit parameters. We also expose that the method can be applicable to every fault location in a circuit and open faults with unknown value. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Defect-Oriented Testing / CMOS Circuits / Interconnect Open Faults / Ramp Voltage / Logic Testing |
| Paper # | DC2004-109 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2005/2/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
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| Assistant | |
| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Interconnect Open Detection by Ramp Voltage Application |
| Sub Title (in English) | |
| Keyword(1) | Defect-Oriented Testing |
| Keyword(2) | CMOS Circuits |
| Keyword(3) | Interconnect Open Faults |
| Keyword(4) | Ramp Voltage |
| Keyword(5) | Logic Testing |
| 1st Author's Name | Yukiya MIURA |
| 1st Author's Affiliation | Graduate School of Engineering, Tokyo Metropolitan University() |
| Date | 2005/2/11 |
| Paper # | DC2004-109 |
| Volume (vol) | vol.104 |
| Number (no) | 664 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |