Presentation 2005/2/11
Statistical Delay Quality Model for Defect Level Estimation
Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara,
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Abstract(in English) In this paper we introduce an evaluation method of statistical delay quality model that reflects fabrication process quality, design delay margin and test timing accuracy. The evaluation method provides a measure that can predict the level of chip defects that cause delay failure, including marginal delay. We can therefore use the method to make test vectors that are effective in terms of both testing cost and chip quality. The results of experiments using ISCAS89 benchmark data and some large industrial design data reflect various characteristics of our evaluation method of statistical delay quality model.
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Keyword(in English) delay test / at-speed test / defect level / delay quality / quality model
Paper # DC2004-108
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Conference Date 2005/2/11(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Statistical Delay Quality Model for Defect Level Estimation
Sub Title (in English)
Keyword(1) delay test
Keyword(2) at-speed test
Keyword(3) defect level
Keyword(4) delay quality
Keyword(5) quality model
1st Author's Name Yasuo Sato
1st Author's Affiliation Semiconductor Technology Academic Research Center()
2nd Author's Name Shuji Hamada
2nd Author's Affiliation Semiconductor Technology Academic Research Center
3rd Author's Name Toshiyuki Maeda
3rd Author's Affiliation Semiconductor Technology Academic Research Center
4th Author's Name Atsuo Takatori
4th Author's Affiliation Semiconductor Technology Academic Research Center
5th Author's Name Seiji Kajihara
5th Author's Affiliation Department of Computer Sciences and Electronics, Kyushu Institute of Technology
Date 2005/2/11
Paper # DC2004-108
Volume (vol) vol.104
Number (no) 664
Page pp.pp.-
#Pages 6
Date of Issue