| Presentation | 2005/2/11 Test Compaction for Path Delay Faults in Deep Submicron LSIs Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths selected with a criterion. While the proposed method generates each two-pattern test for more than one fault in the fault list, secondary target faults are selected from the fault list such that many other faults, which may not be included in the fault list, are detected by the test pattern. Even if faults on long paths in a manufactured circuit are not included in the fault list due to a process variation or noise, the compact test set would detect the untargeted faults. Experimental results show that the proposed method can generate a compact test set and it detects longer untargeted path delay faults. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Delay testing / Test compaction / Path delay fault / Process variation |
| Paper # | DC2004-107 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2005/2/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Test Compaction for Path Delay Faults in Deep Submicron LSIs |
| Sub Title (in English) | |
| Keyword(1) | Delay testing |
| Keyword(2) | Test compaction |
| Keyword(3) | Path delay fault |
| Keyword(4) | Process variation |
| 1st Author's Name | Seiji Kajihara |
| 1st Author's Affiliation | Kyushu Institute of Technology() |
| 2nd Author's Name | Masayasu Fukunaga |
| 2nd Author's Affiliation | Kyushu Institute of Technology |
| 3rd Author's Name | Xiaoqing Wen |
| 3rd Author's Affiliation | Kyushu Institute of Technology |
| 4th Author's Name | Toshiyuki Maeda |
| 4th Author's Affiliation | Semiconductor Technology Academic Research Center |
| 5th Author's Name | Shuji Hamada |
| 5th Author's Affiliation | Semiconductor Technology Academic Research Center |
| 6th Author's Name | Yasuo Sato |
| 6th Author's Affiliation | Semiconductor Technology Academic Research Center |
| Date | 2005/2/11 |
| Paper # | DC2004-107 |
| Volume (vol) | vol.104 |
| Number (no) | 664 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |