| Presentation | 2005/2/11 Test Scheduling for Multi-clock Domain SoC with Power Constraints Kimihiko MASUDA, Tomokazu YONEDA, Hideo FUJIWARA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We propose wrapper/TAM design and test scheduling algorithm to minimize test application time for multi-clock domain SoC that consists of cores with different operational frequency during test. In the proposed method, we consider the following constraints : the number of test pins and maximun available power consumption of a givenSoC, operational frequency of core during test, and operational frequency of ATE. We use TDM (Test Data Multiplexing) to solve the frequency gap between core and ATE. Moreover, we use TDM to reduce the power consumption of cores while keeping test time of the cores. Experimental results show the effectiveness of our method not only for multi-clock domain SoC, but also for single-clock domain SoCs with power constraints. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | multi-clock domain SoC / power consumption / test data multiplexing / test scheduling |
| Paper # | DC2004-103 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2005/2/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Test Scheduling for Multi-clock Domain SoC with Power Constraints |
| Sub Title (in English) | |
| Keyword(1) | multi-clock domain SoC |
| Keyword(2) | power consumption |
| Keyword(3) | test data multiplexing |
| Keyword(4) | test scheduling |
| 1st Author's Name | Kimihiko MASUDA |
| 1st Author's Affiliation | Nara Institute of Science and Technology() |
| 2nd Author's Name | Tomokazu YONEDA |
| 2nd Author's Affiliation | Nara Institute of Science and Technology |
| 3rd Author's Name | Hideo FUJIWARA |
| 3rd Author's Affiliation | Nara Institute of Science and Technology |
| Date | 2005/2/11 |
| Paper # | DC2004-103 |
| Volume (vol) | vol.104 |
| Number (no) | 664 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |