Presentation 2005/2/11
A Reconfigurable Union Wrapper for SoC Test Scheduling
Masahiro IMANISHI, Tomokazu YONEDA, Hideo FUJIWARA,
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Abstract(in English) This paper presents a reconfigurable union wrapper that can wrap multiple cores into single wrapper design. Moreover, we present a test scheduling algorithm to minimize a test application time using the proposed reconfigurable union wrapper. The proposed heuristic algorithm can achieve short test application time with low computational cost. Experimental results for the ITC'02 SOC Benchmarks show the effectiveness of our approach.
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Keyword(in English) system-on-a-chip / test scheduling / reconfigurable union wrapper / test access mechanism
Paper # DC2004-102
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Committee DC
Conference Date 2005/2/11(1days)
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Paper Information
Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Reconfigurable Union Wrapper for SoC Test Scheduling
Sub Title (in English)
Keyword(1) system-on-a-chip
Keyword(2) test scheduling
Keyword(3) reconfigurable union wrapper
Keyword(4) test access mechanism
1st Author's Name Masahiro IMANISHI
1st Author's Affiliation Nara Institute of Science and Technology()
2nd Author's Name Tomokazu YONEDA
2nd Author's Affiliation Nara Institute of Science and Technology
3rd Author's Name Hideo FUJIWARA
3rd Author's Affiliation Nara Institute of Science and Technology
Date 2005/2/11
Paper # DC2004-102
Volume (vol) vol.104
Number (no) 664
Page pp.pp.-
#Pages 6
Date of Issue