| Presentation | 2005/2/11 Acceleration of Test Generation for Sequential Circuit Using Knowledge Obtained from Synthesis for Testability Masato NAKAZATO, Satoshi OHTAKE, Hideo FUJIWARA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose an integrated Synthesis for Testability (SfT) and a test generation method of Finite State Machines (FSM). The SfT method produces an easily testable sequential circuit for a given FSM description of the circuit while taking into consideration the features of a high speed sequential test generator. The SfT method guarantees that the test generator will be able to find a state distinguishing sequence by making the FSM reduced. Whereas, the performance of the test generator is improved as it uses the state justification sequence extracted from the completely specified state transition function of the FSM produced by the synthesizer. Experimental results show that the proposed integrated approach can completely identify each fault in the circuit, detectable or redundant, and can achieve this 100% fault efficiency in a short test generation time. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | sequential circuit / test generation / synthesis for testability / finite state machine / knowledge |
| Paper # | DC2004-97 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2005/2/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Acceleration of Test Generation for Sequential Circuit Using Knowledge Obtained from Synthesis for Testability |
| Sub Title (in English) | |
| Keyword(1) | sequential circuit |
| Keyword(2) | test generation |
| Keyword(3) | synthesis for testability |
| Keyword(4) | finite state machine |
| Keyword(5) | knowledge |
| 1st Author's Name | Masato NAKAZATO |
| 1st Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology() |
| 2nd Author's Name | Satoshi OHTAKE |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| 3rd Author's Name | Hideo FUJIWARA |
| 3rd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| Date | 2005/2/11 |
| Paper # | DC2004-97 |
| Volume (vol) | vol.104 |
| Number (no) | 664 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |