| Presentation | 2005/2/11 Equivalence of Sequential Transition Test Generation and Constrained Combinational Stuck-at Test Generation Tsuyoshi IWAGAKI, Satoshi OHTAKE, Hideo FUJIWARA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, a transition test generation method for acyclic sequential circuits is presented. In this method, to generate a test sequence for a transition fault in a given acyclic sequential circuit, constrained combinational stuck-at test generation is performed on its double time-expansion model, which is composed of two copies of a time-expansion model of the given circuit. This method can guarantee complete fault efficiency, i.e., it can generate test sequences for all the testable transition faults and can identify all the untestable transition faults in a given acyclic sequential circuit. Experimental results show that our method can achieve high fault efficiency with drastically short test generation time compared with that obtained by conventional methods. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | sequential transition test generation / acyclic sequential circuit / constrained combinational stuck-at test generation / double time-expansion model / complete fault efficiency |
| Paper # | DC2004-96 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2005/2/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Equivalence of Sequential Transition Test Generation and Constrained Combinational Stuck-at Test Generation |
| Sub Title (in English) | |
| Keyword(1) | sequential transition test generation |
| Keyword(2) | acyclic sequential circuit |
| Keyword(3) | constrained combinational stuck-at test generation |
| Keyword(4) | double time-expansion model |
| Keyword(5) | complete fault efficiency |
| 1st Author's Name | Tsuyoshi IWAGAKI |
| 1st Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology() |
| 2nd Author's Name | Satoshi OHTAKE |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| 3rd Author's Name | Hideo FUJIWARA |
| 3rd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| Date | 2005/2/11 |
| Paper # | DC2004-96 |
| Volume (vol) | vol.104 |
| Number (no) | 664 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |