| Presentation | 2005/2/11 Design for Hierarchical Testability for Reducing Hold Controls Naoki OKAMOTO, Hideyuki ICHIHARA, Tomoo INOUE, Toshinori HOSOKAWA, Hideo FUJIWARA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Hierarchical test generation is an efficient method of test generation for VLSI circuits. In this work, we propose a reduction method of hold controls for hierarchical testable design based on strong testability of register-transfer level (RTL) datapaths. We improve the algorithm, which is a part of the DFT/test plan generation algorithm [4], for generating a controlling forest without time conflict. The improved method attempts to share hold registers with as many modules in time conflict as possible, while reducing the number of time conflicts. As a result, it can reduce the number of controls for hold registers, even though the number of time conflicts may increase. Experimental results show that the proposed algorithm is effective in reducing the number of controls of hold registers, so that it can reduce hardware overhead of the test controller. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Design for Testability / Hierarchical test generation / strong testability / datapath / test plan |
| Paper # | DC2004-94 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2005/2/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design for Hierarchical Testability for Reducing Hold Controls |
| Sub Title (in English) | |
| Keyword(1) | Design for Testability |
| Keyword(2) | Hierarchical test generation |
| Keyword(3) | strong testability |
| Keyword(4) | datapath |
| Keyword(5) | test plan |
| 1st Author's Name | Naoki OKAMOTO |
| 1st Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University() |
| 2nd Author's Name | Hideyuki ICHIHARA |
| 2nd Author's Affiliation | Faculty of Information Sciences, Hiroshima City University |
| 3rd Author's Name | Tomoo INOUE |
| 3rd Author's Affiliation | Faculty of Information Sciences, Hiroshima City University |
| 4th Author's Name | Toshinori HOSOKAWA |
| 4th Author's Affiliation | College of Industrial Technology, Nihon University |
| 5th Author's Name | Hideo FUJIWARA |
| 5th Author's Affiliation | Graduate School of Info. Science, Nara Institute of Science and Technology |
| Date | 2005/2/11 |
| Paper # | DC2004-94 |
| Volume (vol) | vol.104 |
| Number (no) | 664 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |