| Presentation | 2005/2/11 Design for Partially Strong Testability of Data Paths to Guarantee Complete Fault Efficiency Hiroyuki IWATA, Tomokazu YONEDA, Satoshi OHTAKE, Hideo FUJIWARA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a design-for-testability method based on non-scan approach to guarantee complete fault efficiency for register transfer level data paths. In the paper, we first define partially strong testability of register transfer level data paths and then propose a design-for-testability and a test generation method for data paths based on partially strong testability. The hardware overhead of the proposed method is smaller than that of the method based on strong testability because the proposed method guarantees strong testability only for a part of a data path. Further, the proposed method can apply tests at operational speed and acheive complete fault efficiency. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | design-for-testability / data paths / strong testability / partially strong testability / complete fault efficiency |
| Paper # | DC2004-92 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2005/2/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design for Partially Strong Testability of Data Paths to Guarantee Complete Fault Efficiency |
| Sub Title (in English) | |
| Keyword(1) | design-for-testability |
| Keyword(2) | data paths |
| Keyword(3) | strong testability |
| Keyword(4) | partially strong testability |
| Keyword(5) | complete fault efficiency |
| 1st Author's Name | Hiroyuki IWATA |
| 1st Author's Affiliation | Graduate School of Information, Nara Institute of Science and Technology() |
| 2nd Author's Name | Tomokazu YONEDA |
| 2nd Author's Affiliation | Graduate School of Information, Nara Institute of Science and Technology |
| 3rd Author's Name | Satoshi OHTAKE |
| 3rd Author's Affiliation | Graduate School of Information, Nara Institute of Science and Technology |
| 4th Author's Name | Hideo FUJIWARA |
| 4th Author's Affiliation | Graduate School of Information, Nara Institute of Science and Technology |
| Date | 2005/2/11 |
| Paper # | DC2004-92 |
| Volume (vol) | vol.104 |
| Number (no) | 664 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |