| Presentation | 2004/11/24 A Cost-effective Technique to Mitigate Soft Errors in Logic Circuits Luong D. HUNG, Masanori TAKADA, Yi GE, Shuichi SAKAI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The soft error rates (SER) in logic circuits increase quickly as devices scale. Existing techniques to mitigate soft errors hi logic circuits often incur large overheads. In this work, we propose a 'lightweight' technique that detects soft errors in logic circuits, utilizing the concept of temporal sampling. The technique adds some modifications to the conventional pipeline to allow data to be sampled twice in time and compared for integrity. The area, power, and tuning overheads of modifying a 32-bit multiplier to support the technique are respectively 19.3%, 7.6%, and 6.4%. Comparing to existing soft error detection circuit techniques, our technique incurs lower overheads. The technique is also applicable in scaled process technologies. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Soft error / SER / logic circuit / pipeline / flip flop |
| Paper # | VLD2004-54,ICD2004-140,DC2004-40 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2004/11/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Cost-effective Technique to Mitigate Soft Errors in Logic Circuits |
| Sub Title (in English) | |
| Keyword(1) | Soft error |
| Keyword(2) | SER |
| Keyword(3) | logic circuit |
| Keyword(4) | pipeline |
| Keyword(5) | flip flop |
| 1st Author's Name | Luong D. HUNG |
| 1st Author's Affiliation | Graduate School of Information Science and Technology, The University of Tokyo() |
| 2nd Author's Name | Masanori TAKADA |
| 2nd Author's Affiliation | Graduate School of Information Science and Technology, The University of Tokyo |
| 3rd Author's Name | Yi GE |
| 3rd Author's Affiliation | Graduate School of Information Science and Technology, The University of Tokyo |
| 4th Author's Name | Shuichi SAKAI |
| 4th Author's Affiliation | Graduate School of Information Science and Technology, The University of Tokyo |
| Date | 2004/11/24 |
| Paper # | VLD2004-54,ICD2004-140,DC2004-40 |
| Volume (vol) | vol.104 |
| Number (no) | 481 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |