| Presentation | 2004/11/24 High-Speed Logic Circuit Technology with Asymmetric Slope Transition Masao MORIMOTO, Makoto NAGATA, Kazuo TAKI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Differential logic circuits with asymmetric signal transition surpass the highest speed that conventional CMOS logic circuits can achieve, resulting from deeply shortened rise time along with reasonably slowed fall time. ASD-CMOS (Asymmetric Slope Differential CMOS) is a static logic and ASDDL (Asymmetric Slope Differential Dynamic Logic) is a dynamic logic without per-gate synchronous clock signal, each of which needs two-phase operation as well as differential signaling. ASDDL/ASD-CMOS achieves smaller area and lower power than conventional dynamic circuits. ASDDL and ASD-CMOS 16-bit multipliers in a 0.18-μm CMOS technology demonstrates 1.82 nsec and 1.78 nsec, which corresponds to 96% and 94% of DCVS-DOMINO, respectively. The area was 92% and 97% of that in DCVS-DOMINO implementation, and the power consumption reduces to 20% and 2%, respectively. A prototype ASD-CMOS 16-bit multiplier with built-in test circuitry fabricated in a 0.13-μm CMOS technology operates with the delay time of 1.57 nsec at 1.2 V. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | ASDDL / ASD-CMOS / asymmetric slope / differential logic / high speed |
| Paper # | VLD2004-53,ICD2004-139,DC2004-39 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2004/11/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High-Speed Logic Circuit Technology with Asymmetric Slope Transition |
| Sub Title (in English) | |
| Keyword(1) | ASDDL |
| Keyword(2) | ASD-CMOS |
| Keyword(3) | asymmetric slope |
| Keyword(4) | differential logic |
| Keyword(5) | high speed |
| 1st Author's Name | Masao MORIMOTO |
| 1st Author's Affiliation | Graduate School of Science and Technology, Kobe University() |
| 2nd Author's Name | Makoto NAGATA |
| 2nd Author's Affiliation | Department of Computer and Systems Engineering, Kobe University |
| 3rd Author's Name | Kazuo TAKI |
| 3rd Author's Affiliation | Department of Computer and Systems Engineering, Kobe University |
| Date | 2004/11/24 |
| Paper # | VLD2004-53,ICD2004-139,DC2004-39 |
| Volume (vol) | vol.104 |
| Number (no) | 481 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |