| Presentation | 2004/8/13 65nm-node CMOS Process for Low Power Devices : LOP Specific Ultra-Shallow Junction Technology, and LSTP Specific HfSiON Transistor Technology Fumio OOTSUKA, Akira MINEJI, Yasuyuki TAMURA, Takaoki SASAKI, Hiroji OZAKI, Mitsuo YASUHIRA, Tsunetoshi ARIKADO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Flash lamp annealing increases the drivability of the pFETs with the shallow extension fabricated by SPE growth without deteriorating Vth roll-off. A high switching speed suitable for 65nm-node LOP has been obtained at the gate length of 35nm by using SPE+FLA activation process. For LSTP devices, HfSiON transistors with EOT=1.5nm have been developed. Fermi-Level Pinning was improved by depositing thin SiN'cap on HfSiON. Tolerable NBTI/PBTI lifetime has been obtained at 1.1V supply voltage. |
| Keyword(in Japanese) | (See Japanese page) |
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| Paper # | SDM2004-149,ICD2004-91 |
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| Committee | ICD |
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| Conference Date | 2004/8/13(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 65nm-node CMOS Process for Low Power Devices : LOP Specific Ultra-Shallow Junction Technology, and LSTP Specific HfSiON Transistor Technology |
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| 1st Author's Name | Fumio OOTSUKA |
| 1st Author's Affiliation | Research Dept. 1, Semiconductor Leading Edge Technologies, Inc.(Selete)() |
| 2nd Author's Name | Akira MINEJI |
| 2nd Author's Affiliation | Research Dept. 1, Semiconductor Leading Edge Technologies, Inc.(Selete) |
| 3rd Author's Name | Yasuyuki TAMURA |
| 3rd Author's Affiliation | Research Dept. 1, Semiconductor Leading Edge Technologies, Inc.(Selete) |
| 4th Author's Name | Takaoki SASAKI |
| 4th Author's Affiliation | Research Dept. 1, Semiconductor Leading Edge Technologies, Inc.(Selete) |
| 5th Author's Name | Hiroji OZAKI |
| 5th Author's Affiliation | Research Dept. 1, Semiconductor Leading Edge Technologies, Inc.(Selete) |
| 6th Author's Name | Mitsuo YASUHIRA |
| 6th Author's Affiliation | Research Dept. 1, Semiconductor Leading Edge Technologies, Inc.(Selete) |
| 7th Author's Name | Tsunetoshi ARIKADO |
| 7th Author's Affiliation | Research Dept. 1, Semiconductor Leading Edge Technologies, Inc.(Selete) |
| Date | 2004/8/13 |
| Paper # | SDM2004-149,ICD2004-91 |
| Volume (vol) | vol.104 |
| Number (no) | 251 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |