Presentation	2004/8/13 High-Resolution On-Chip Propagation Delay Detector for Measuring Within-Chip and Chip-to-Chip Variation Takashi Matsumoto,
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Abstract(in English)	We propose a circuit that can measure the propagation delay of a logic circuit directly even for one fan-out 1 inverter of CMOS 90 nm node technology. We obtained high-resolution (1 ps) by converting the propagation delay to the control voltage of the voltage-controlled delay line (VCDL) in Delay-Locked Loop (DLL). The circuit was fabricated with 90 nm CMOS technology and we have verified the function. This circuit can be used for measuring within-chip and chip-to-chip variation that is important for design automation in sub-100nm technology.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	propagation delay / DLL / voltage sampler / CMOS / sub-100nm / within-chip variation / design automation / DFM
Paper #	SDM2004-140,ICD2004-82
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Conference Information
Committee	ICD
Conference Date	2004/8/13(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	High-Resolution On-Chip Propagation Delay Detector for Measuring Within-Chip and Chip-to-Chip Variation
Sub Title (in English)
Keyword(1)	propagation delay
Keyword(2)	DLL
Keyword(3)	voltage sampler
Keyword(4)	CMOS
Keyword(5)	sub-100nm
Keyword(6)	within-chip variation
Keyword(7)	design automation
Keyword(8)	DFM
1st Author's Name	Takashi Matsumoto
1st Author's Affiliation	Fujitsu Laboratories Ltd.()
Date	2004/8/13
Paper #	SDM2004-140,ICD2004-82
Volume (vol)	vol.104
Number (no)	251
Page	pp.pp.-
#Pages	6
Date of Issue